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upf architecture

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  1. Power Domain:
    • In UPF, a power domain is a group of related power supply networks and associated logic that can be managed together for power control purposes.
    • Power domains are defined to control the power state of specific portions of the design independently.
  2. Primary Power Domain:
    • This is the main power domain in the design that encompasses the entire chip. It typically includes the main power supplies and serves as a reference for other power domains.
  3. Power States:
    • UPF defines various power states that a power domain or a part of the design can be in. These states include ON, OFF, RETENTION, and others.
    • ON state implies normal operation, OFF state implies complete power shutdown, and RETENTION state implies maintaining certain state information while minimizing power.
  4. Power Supply Network:
    • UPF describes the power supply network for each power domain. It includes details about power rails, power supplies, and connections.
  5. Isolation:
    • UPF allows for the specification of isolation cells and strategies. Isolation is used to cut off power to certain parts of the design when they are in a low-power state.
  6. Power Intent Commands:
    • UPF uses commands to express the power intent. These commands include specifications about when to switch power domains on or off, when to apply isolation, and how to transition between power states.
  7. Power States at Hierarchical Levels:
    • UPF supports hierarchical descriptions of power intent. This means that power states and commands can be specified not only at the chip level but also at various levels of hierarchy within the design.
  8. Anchors:
    • Anchors in UPF are used to specify reference points for power state transitions. They help ensure a smooth transition between different power states.
  9. Sequential and Combinational Logic:
    • UPF allows the description of power intent for both sequential and combinational logic. Sequential elements may have different power characteristics compared to combinational logic, and UPF provides mechanisms to capture this.
  10. Verification and Validation:
    • UPF includes features to enable verification and validation of the power intent. This is crucial to ensure that the design meets power requirements and behaves as expected during different power scenarios.

UPF architecture provides a standardized way to describe how power is managed in an IC design. It encompasses power domains, states, supply networks, isolation, and commands to specify the power intent at various levels of hierarchy. This standardized format facilitates interoperability between different tools in the design flow and supports the implementation of low-power design methodologies.